1. Field of the Invention
This invention relates to semiconductor integrated circuits, and more particularly, to a clock generating apparatus that controls skew between two-phase non-overlapping clocks, used as inputs of latch or flip-flop circuits.
2. Description of the Related Art
Recently, most chips are designed with synchronous circuits as a basic building block. Among them, a number of chips are using two or more non-overlapping clocks. It is common and general phenomenon that the circuit operation in a synchronous chip would not operate properly by a clock skew. Moreover when a chip is designed with a number of clocks, many problems are occur by a skew between clocks. If the skew between the two clocks is not laid within a non-overlapping period, then overlapping clock period will occur and chip will do not operate properly for this overlapping period. Thus, the accuracy of a clock skew is very important problem in chip design. In order for the most prior art to solve the clock skew problem, the important points are arranging of a hierarchical clock tree between the clock inputs of a latch or flip-flop, the destination point from the clock source, and placing and routing of each clock buffer.
However, the major disadvantage in the prior art is that the clock skew would not reduced to a satisfactory level in generating, placing and routing steps of clock tree. That is because though the total delay of the clock should be accurately considered in generating, placing and routing steps of the clock tree, but this delay much depends on clock itself, other circuit cell and geometrical shape of metal routing of other signals.